NXP Semiconductors /LPC13xx /SYSCON /SSP0CLKDIV

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as SSP0CLKDIV

31282724232019161512118743000000000000000000000000000000000000000000DIV0RESERVED

Description

SSP clock divder

Fields

DIV

SSP_PCLK clock divider values. 0: Disable SSP0_PCLK. 1: Divide by 1. to 255: Divide by 255.

RESERVED

Reserved

Links

()